Digital Evaluation Engineer

Responsibilities:

	Development of hardware and software for evaluating digital ASIC cores and ASIC devices
	Work with digital designers and system engineers throughout development cycle
	Provide FPGA based emulation of digital circuits for ASIC verification and system development
	Assist in algorithm development and debug

Requirements:

	BSEE and a minimum of 5 years experience in a CMOS, mixed-signal design or high speed FPGA based enviroment
	Object oriented coding, IDL, Altera/Xilinx development tools, Cadence a plus
	Laboratory equipment such as power supplies, oscilloscopes, logic analyzers, etc. for digital electronic testing at up to 400MHz
	Must be able to work independently as well as in a team, be highly organized, have good communication skills
	Good verbal and written English is required